Closing the SoC Design Gap

E mbedded systems are ubiquitous , and they represent the major market for microprocessors. In fact, more than one billion microprocessors find their way into embedded systems every year, and this number will continue to grow rapidly. One reason for this phenomenon is that intense competition among man-ufacturers—especially for mainstream consumer products—has shortened the life cycles for products that use embedded systems. For example, cell phone manufacturers now release two major new product lines each year compared with only one just a few years ago. At the same time, product function-ality and hence the complexity of underlying embedded systems are rapidly increasing. Cell phones, for instance, now provide many functions beyond their core functionality, such as Web browsing capabilities, personal digital assistant functions, short message services , and even gaming. Shorter product life cycles and increased functionality create a demand that matches well with the International Technology Roadmap for Semiconductors' prediction of 1 billion transistors on a single chip within this decade. However, current mainstream system-on-chip (SoC) designs do not yet fully exploit the 100 million transistors per chip possible with today's mainstream silicon technology. Electronic system-level (ESL) design tools offer a way of addressing this " crisis of complexity, " as Gartner Dataquest's Gary Smith described it at this year's Design Automation Conference. Without extensive use of ESL design tools, though, it is predicted that by 2005, when 250 million gates per SoC become feasible, most SoCs would use only around 50 million. The increasing gap between silicon technology and actual SoC design complexities is one indicator of the need for ESL tools combined with intense use of off-the-shelf components. Another is a decrease in the number of design starts for application-specific integrated circuits relative to the number for application-specific standard prod-ucts—that is, customized ICs sold to more than one customer. In fact, ASSP design starts are currently outpacing ASIC design starts by about 5,000 to 4,000, respectively (B. Lewis and S. Hsu, ASIC/SOC: Rebuilding after the Storm, market report, Gartner, 2002). The increasingly high nonrecurring engineering (NRE) costs of migrating to 130-nanometer ASIC technologies only amortize for very large volumes— perhaps several million units, depending on the design. Early embedded SoCs were of low complexity, typically comprising one or two programmable processing units—say, a microcontroller and a digital signal processor—plus some custom hardware, peripherals, and memory. Current SoC designs, however , use a rapidly increasing number of processing …